In present semiconductor technology, complementary metal oxide semiconductor (CMOS) devices, such as nFETs or pFETs, are typically fabricated upon semiconductor wafers, such as Si, that have a single crystal orientation. In particular, most of today's semiconductor devices are built upon Si having a (100) crystal orientation.
Electrons are known to have a high mobility for a (100) Si surface orientation, but holes are known to have high mobility for a (110) surface orientation. That is, hole mobility values on (100) Si are roughly 2×-4× lower than the corresponding electron mobility for this crystallographic orientation. To compensate for this discrepancy, pFETs are typically designed with larger widths in order to balance pull-up currents against the nFET pull-down currents and achieve uniform circuit switching. pFETs having larger widths are undesirable since they take up a significant amount of chip area.
On the other hand, hole mobilities on (110) Si are 2× higher than on (100) Si; therefore, pFETs formed on a (110) surface will exhibit significantly higher drive currents than pFETs formed on a (100) surface. Unfortunately, electron mobilities on (110) Si surfaces are significantly degraded compared to (100) Si surfaces.
As can be deduced from the above discussion, the (110) Si surface is optimal for pFET devices because of excellent hole mobility, yet such a crystal orientation is completely inappropriate for nFET devices. Instead, the (100) Si surface is optimal for nFET devices since that crystal orientation favors electron mobility.
Methods have been described to form planar hybrid substrates with different surface orientations through wafer bonding. In such endeavors, the planar hybrid substrate is obtained mainly through semiconductor-to-insulator, or insulator-to-insulator wafer bonding to achieve pFETs and nFETs on their own optimized crystal orientation for high performance device manufacture. However, at least one type of MOSFET (either pFETs or nFETs) is on a semiconductor-on-insulator (SOI), while the other type of MOSFET is either on a bulk semiconductor or an SOI with a thicker SOI film.
A method to fabricate planar bulk-like nFETs and pFETs on a hybrid orientated substrate through silicon-to-silicon direct bonding to achieve both kinds of devices on their optimized orientation for highest performance has been disclosed, for example, in U.S. application Ser. No. 10/799,380, filed Mar. 12, 2004, now U.S. Pat. No. 7,023,057 and Ser. No. 10/696,634, filed Oct. 29, 2003, now U.S. Pat. No. 7,023,055.
In today's conventional CMOS integrated circuits (ICs) with bulk-like pFETs and nFETs, isolation usually is achieved by shallow trench isolation (STI). Such a structure is shown, for example, in FIG. 1. In the prior art structure, reference numeral 100 denotes the semiconductor substrate, reference numeral 102 denotes a p-well, reference numeral 104 denotes an n-well, reference numeral 106 denotes shallow trench isolation (STI), reference numeral 108 denotes an nFET, reference numeral 110 denotes a pFET, reference numeral 112 denotes a p-well (or substrate) contact and reference numeral 114 denotes an n-well (or substrate) contact.
In the prior art structure shown in FIG. 1, each STI 106 is formed by first etching relatively shallow trenches (on the order of about 0.3 to about 0.5 μm), which are shallower than the depth of the well, into the semiconductor substrate 100 and then each trench is filled with a trench dielectric material such as an oxide. The surface is planarized after trench fill to complete the isolation structure. However, as the ground rule shrinks, the width of the STI reduces, resulting in a higher aspect ratio. Thus, it has become more difficult to obtain void- and seam-free trench fill.
On the other hand, CMOS isolation exists not only between like-kind of devices, e.g., between two nFETs or two pFETs, but also between opposite polarity, i.e., between nFETs and pFETs which are separated by at least one well. In general, isolation for the latter, including nFET and pFET isolation and latch-up, consumes much more chip area and requires much deeper STI depth.
In view of the above discussion, there is a need for providing a structure having both pFETs and nFETs on a hybrid oriented (HOT) substrate with different crystal orientations, wherein both the pFET and nFET devices are bulk-like, and wherein the pFET and nFET devices are separated from devices with opposite polarity.